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Design Compilerhttps://blog.csdn.net/weixin_45791458/category_12738116.html
在静态时序分析：传播延迟与转换时间一文中，已经介绍了转换时间阈值和转换时间减免系数的概念，如果一个设计中两个单元的转换时间阈值和转换时间减免系数不一致会发生什么？本文将以Design Compiler对此进行说明。
假设存在以下两个逻辑库，它们的转换时间阈值和转换时间减免系数如下所示。
// 库fast_lack slew_lower_threshold_pct_fall : 30.0; slew_upper_threshold_pct_fall : 70.0; slew_lower_threshold_pct_rise : 30.0; slew_upper_threshold_pct_rise : 70.0; input_threshold_pct_fall : 50.0; input_threshold_pct_rise : 50.0; output_threshold_pct_fall : 50.0; output_threshold_pct_rise : 50.0; slew_derate_from_library : 0.5;// 库fast_slew slew_lower_threshold_pct_fall : 10.0; slew_upper_threshold_pct_fall : 90.0; slew_lower_threshold_pct_rise : 10.0; slew_upper_threshold_pct_rise : 90.0; input_threshold_pct_fall : 50.0; input_threshold_pct_rise : 50.0; output_threshold_pct_fall : 50.0; output_threshold_pct_rise : 50.0; slew_derate_from_library : 0.5;图1 一个简单的电路
对于图1所示的电路，将这两个逻辑库都加入link_library（这可能会导致警告Warning: The trip points for the library named fast_slew differ from those in the library named fast_lack. (TIM-164)，并设法使单元u1被link到fast_lack库，而单元u2被link到fast_slew库，如下报告所示。
**************************************** Report : cell Design : test Version: W-2024.09-SP2 Date : Wed Apr 16 15:23:48 2025 **************************************** Attributes: b - black box (unknown) h - hierarchical n - noncombinational r - removable u - contains unmapped logic Cell Reference Library Area Attributes -------------------------------------------------------------------------------- u1 CLKINVX1 fast_lack 2.116800 u2 CLKBUFX1 fast_slew 2.822400 -------------------------------------------------------------------------------- Total 2 cells 4.939200此时使用下面的命令报告线网t的转换时间的计算过程。
report_cell_calculation -from [get_pins u1/Y] -to [get_pins u2/A]**************************************** Report : delay_calculation Design : test Version: W-2024.09-SP2 Date : Wed Apr 16 15:28:04 2025 **************************************** From pin: u1/Y To pin: u2/A Main Library Units: 1ns 1pF 1kOhm Operating Conditions: fast Library: fast_lack Wire Load Model Mode: top arc type: net Balanced case tree RC delay: (r_wire/load_count) * (c_pin + c_wire/load_count) rise: (0 / 1) * (0.001682 + (0 / 1)) fall: (0 / 1) * (0.001682 + (0 / 1)) total delay rise, fall: 0.0000 , 0.0000 Rise Transition Trippoint Adjustment Trippoint Driver Load --------- ------ ----- low 0.30 0.10 high 0.70 0.90 lib_derate 0.50 0.50 Adjustment = ( driver_derate * (load_high - load_low) ) / ( load_derate * (driver_high - driver_low) ) Adjustment = 2 = ( 0.5 * (0.9 - 0.1) ) / ( 0.5 * (0.7 - 0.3) ) Multiplying original transition (0.0125849) by 2 gives 0.0251698 Fall Transition Trippoint Adjustment Trippoint Driver Load --------- ------ ----- low 0.30 0.10 high 0.70 0.90 lib_derate 0.50 0.50 Adjustment = ( driver_derate * (load_high - load_low) ) / ( load_derate * (driver_high - driver_low) ) Adjustment = 2 = ( 0.5 * (0.9 - 0.1) ) / ( 0.5 * (0.7 - 0.3) ) Multiplying original transition (0.0124807) by 2 gives 0.0249614可以看出，由于驱动引脚和负载引脚的转换时间阈值不同，Design Compiler使用了转换时间过渡调整(Transition Trippoint Adjustment)，它的计算公式如下所示。
Adjustment = ( driver_derate * (load_high - load_low) ) / ( load_derate * (driver_high - driver_low) )对于单元而言，它的转换时间阈值和转换时间减免系数由其所在的逻辑库决定，但对于输入/输出端口而言呢？
输入/输出端口的转换时间阈值和转换时间减免系数由link_library变量或local_link_library属性（两者统称为link_path）中的第一个逻辑库（即主库）决定。
当主库是fast_lack库时，线网A的转换时间不会发生调整而线网C的转换时间会发生调整，如下所示。
**************************************** Report : delay_calculation Design : test Version: W-2024.09-SP2 Date : Wed Apr 16 15:46:27 2025 **************************************** From port: A To pin: u1/A Main Library Units: 1ns 1pF 1kOhm Operating Conditions: fast Library: fast_lack Wire Load Model Mode: top arc type: net Balanced case tree RC delay: (r_wire/load_count) * (c_pin + c_wire/load_count) rise: (0 / 1) * (0.001572 + (0 / 1)) fall: (0 / 1) * (0.001572 + (0 / 1)) total delay rise, fall: 0.0000 , 0.0000 **************************************** Report : delay_calculation Design : test Version: W-2024.09-SP2 Date : Wed Apr 16 15:46:50 2025 **************************************** From pin: u2/Y To port: C Main Library Units: 1ns 1pF 1kOhm Operating Conditions: fast Library: fast_lack Wire Load Model Mode: top arc type: net Balanced case tree RC delay: (r_wire/load_count) * (c_pin + c_wire/load_count) rise: (0 / 1) * (0 + (0 / 1)) fall: (0 / 1) * (0 + (0 / 1)) total delay rise, fall: 0.0000 , 0.0000 Rise Transition Trippoint Adjustment Trippoint Driver Load --------- ------ ----- low 0.10 0.30 high 0.90 0.70 lib_derate 0.50 0.50 Adjustment = ( driver_derate * (load_high - load_low) ) / ( load_derate * (driver_high - driver_low) ) Adjustment = 0.5 = ( 0.5 * (0.7 - 0.3) ) / ( 0.5 * (0.9 - 0.1) ) Multiplying original transition (0.00864911) by 0.5 gives 0.00432455 Fall Transition Trippoint Adjustment Trippoint Driver Load --------- ------ ----- low 0.10 0.30 high 0.90 0.70 lib_derate 0.50 0.50 Adjustment = ( driver_derate * (load_high - load_low) ) / ( load_derate * (driver_high - driver_low) ) Adjustment = 0.5 = ( 0.5 * (0.7 - 0.3) ) / ( 0.5 * (0.9 - 0.1) ) Multiplying original transition (0.00816404) by 0.5 gives 0.00408202同理，当主库是fast_slew库时，线网C的转换时间不会发生调整而线网A的转换时间会发生调整。
